Modern digital VLSI circuits commonly operate at 1.2 volts or below. However, circuit requirements often call for design and interface with other circuits operating at higher voltages. Example circuits are input/output interface circuits with various off-chip system components such as power management switches, analog input circuits conditioning transducer signals, or output analog drive functions for speakers or other actuators.
One solution to this problem is to use two gate oxide thicknesses and to build both low voltage and high voltage transistors on the same chip. This method increases process complexity and cost. An alternative solution is to use drain extended (DE) MOS transistors that can operate at much higher drain voltages without significant loss in performance and without added process complexity and cost. In a DEMOS transistor a lightly doped extended drain region is constructed between the heavily doped drain contact and the transistor channel region. A depletion region forms in this lightly doped extension causing a voltage drop between the drain contact and the transistor gate. With proper design sufficient voltage may be dropped between the drain contact and the gate to allow a low voltage transistor to be used as a switch for the high voltage.
It is difficult to scale DEMOS transistors because the size of the lightly doped region is determined by the amount of voltage drop required to protect the low voltage gate oxide. To accommodate higher voltages, longer drain extensions or lower doping is required. Longer extensions and lower doping increases the series resistance of the transistor reducing performance.